FIG. 1 illustrates a typical data bus interconnection scheme within a circuit 100. In circuit 100, digital circuit device 102 communicates via Data Bus A with a second digital circuit device 104. This data bus transmits one or more data signals from one digital circuit device to another digital circuit device. The plurality of data signals within Data Bus A may contain data corresponding to any digitally represented value used within these devices. For example, the data signals may contain 32 data bits, D0:D31, that correspond to a processing data path that passes between the devices. Alternatively or in addition, data signals may represent an address data value, Adr0:Adr31, that may be used to address a 32-bit address space. One skilled in the art will recognize that any number of bits may be carried by Data Bus A depending upon a particular application.
A separate clock signal, such as Clock A, is also passed between the digital circuit devices. Clock A provides a reference clock signal that may be used by digital circuit device 104 to sample the data signals transmitted over Data Bus A. Clock A is typically a periodic clock signal that operates at a pre-determined clock frequency that may be used throughout circuit 100. However, a reference clock signal associated with a particular data bus is typically provided for each data bus within circuit 100 to account for different propagation delays or signal latencies that may exist within the transmitting digital circuit devices. As such, Clock A and may differ in phase relative to other bus clock signals that may be present within circuit 100.
FIG. 2 illustrates a set of timing diagrams for Bus A data and Clock A as described above in reference to FIG. 1. Data signals within Data Bus A and Clock A are in phase with each other in that the signals present on Data Bus A may change state on either the rising edge or the falling edge of Clock A. When digital circuit device 104 receives Bus A data signals, I/O interfaces within digital circuit device 104 need to sample these data signals during a time when these signals are both valid and stable. The data signals on Data Bus A become valid and stable after time T0, which corresponds to a rising edge of Clock A. These data signals on Data Bus A may become unstable and/or invalid at time T1, which corresponds to a falling edge of Clock A. Since the data signals on Data Bus A are valid after T0 and before T1, the data signals may be safely sampled at time Tsample, which is a point in time between T0 and T1. Due to system noise, clock jitter, and skew between Clock A and all of the data signals, Tsample should be separated from both T0 and T1. Typically, time Tsample corresponds to a point halfway between T0 and T1 to maximize a setup-and-hold window. For a clock signal having a 50% duty cycle, time Tsample corresponds to a 90-degree phase shift (i.e., a quarter of the period) of Clock A.
Delay-locked loop (DLL) circuits have been typically used to produce digital control signals that identify time Tsample relative to the rising and falling edges of Clock A. These control signals are used by slave delay modules to correctly sample the data signals on Data Bus A. The DLL circuits typically require 4 different delay blocks to implement their functions. These DLL circuits may also suffer from instability issues related to phase comparisons performed on the clock signals. All of these characteristics render prior implementations of the timing control circuits as possibly operating problematically.